Phase-locked-loop circuits or PLL circuits are known in the state of the art which are employed in numerous electronic appliances as, for example, in modulators or demodulators of medium frequency signals or FM signals. Generally a PLL circuit comprises a phase detector having in input a reference frequency and a frequency deriving from a voltage controlled oscillator or VCO, a filter having in input the output signal of the phase detector and outputting a signal in input to the VCO.
A parameter of the PLL circuits is the lock time, that is the time period employed by the circuit to obtain that the output frequency of the VCO becomes equal to the reference frequency. The lock time is inversely proportional to the bandwidth of the circuit; for the PLL circuits used, for example, in FM modulators where the bandwidth of the PLL circuit is about 10 Hz, the lock time is high, that is of some seconds.
Also, during the lock phase of the PLL circuit, the output frequency changes thereby producing interferences in adjacent channels, in the case of a multi-channel FM modulator, and it produces higher noise in the receiver channel. The lock time should be kept low for reducing said perturbations.
A known circuit that lowers the lock time is the PLL circuit which uses a charge pump as shown in FIG. 1. Said circuit comprises a digital phase/frequency detector or PFD (Phase Frequency Detector) 4 having in input a digital reference frequency Fref1 and a digital frequency fv and which has two outputs UP and DOWN to be enabled if the reference frequency Fref1 is respectively higher or lower than the frequency fv. The two outputs UP and DOWN control respective current generators adapted to send a current to a filter 1 having a narrow bandwidth; the phase detector 4 and the current generators act as a current-pump charger. The output voltage signal of the filter 1 is the control signal of the VCO 2, which outputs a frequency of Fout, which is in input to a frequency divider 3 for obtaining the frequency fv. The increase of the current in input to the filter allows an increase of the bandwidth of the filter 1 and a decrease of the lock time. After the lock phase, the charge pump's current is turned back to its normal value to assure the stability of the PLL circuit.
Said circuit is of easy design and the charge pump's current can be controlled easily by means of a microcontroller; however, the circuit has a reduced stability both in the lock phase and during the other successive phases and it may also be difficult to optimize the current-boost time for reducing the lock time to its minimum.
Another circuit solution with a PLL is described in U.S. Pat. No. 5,631,601, which is incorporated by reference. Said patent discloses a PLL circuit adapted to demodulate a FM carrier wave; the circuit comprises a phase detector and a VCO having in input the output signal of the phase detector and adapted to provide a signal in input to the phase detector for comparison with said FM carrier wave. The PLL circuit comprises a variable gain circuit operable to select a desired gain for the PLL and to select a bandwidth for demodulation by the circuit. The circuit of the U.S. Pat. No. 5,631,601 comprises a synthesizer adapted to regulate the PLL at a given frequency; the synthesizer provides a voltage signal in input to the VCO to bring the output frequency of the VCO equal to that of the required carrier. The synthesizer is a circuital element which is of complex provision and requires the use of a determined space in the chip wherein the PLL is implemented.